1. Field of the Invention
The present invention relates to a converting method of vertical data/horizontal data used in a field of data communication and a circuit use in conversion.
2. Description of the Relevant Art
In a field of data communication, conversions of vertical data/horizontal data are performed in parity operation, parity error check, data multiplexing and data separation of time slot interchange.
FIG. 1 is a block diagram of a conventional vertical data/horizontal data converting circuit and FIG. 2 is timing charts thereof. In FIG. 2, the vertical bit number N of data to be converted is 2 and the horizontal bit number M is 3.
Bit serial data a(1) is inputted to a shift register 10 in synchronism with a clock CK and shifted sequentially. Every time M-bit data are inputted, the M-bit data Q(1) to Q(M) are inputted to an M-bit flip-flop 20. SP represents a timing signal of data set to the flip-flop 20. The output of the flip-flop 20 is M-bit parallel data converted from input serial data. The parallel data is inputted to a selector 300. Serial parallel converting circuits having the same configuration are provided by the number N for every input lines, and the parallel conversion data of input data a(2) to a (N) are inputted to the selector 300. ST represents a select signal of the selector 300, and data of N number of flip-flop 20 are selected and outputted sequentially from the selector 300 in synchronism with the select signal ST.
Operation of this circuit is described in detail. In FIG. 2, input data a(1) and a(2) are specified by "a" and three subscripts such as aXYZ. X represents bit serial data frame number, Y represents line number (N=1, 2) and Z represents data number (M=1, 2, 3) in the same frame.
Since such input data a(1), a(2) which are to be regarded as horizontal data are sequentially inputted to the shift register 10 by the clock CK, contents of the M=3-bit shift register 10 change as FIGS. 2(a), (b). Since the timing signal SP is given at the rate of one pulse in every three pulses of the clock CK, contents of the 3-bit flip-flop 20 change as FIGS. 2(c), (d). Then, it is time-division multiplexed into the vertical data shown in FIG. 2(c) by the select signal ST which is synchronous with the clock CK.
FIG. 3 shows a vertical data/horizontal data converting circuit disclosed in the Japanese Patent Application No. Sho 61-20431. The circuit comprises a latch matrix 400 consisting of latches 40p which are of same number as that of the vertical data .times. horizontal data. The vertical (or horizontal) data to be converted are latched by the latch matrix 400. The latch data are read out into a circuit network 500 by giving address signals of the latches 40p in a predetermined sequence. Data are arranged in the circuit network 500 so as to enable required conversions.
In the circuit shown in FIG. 1, M units of flip-flops are necessary for the shift register 10. The flip-flop 20 is also necessary for M bits. Thus, 2 MN units of flip-flops are necessary in total, the fact resulting in a complicated circuit configuration.
On the circuit shown in FIG. 3, since data to be converted which have been latched temporarily by the latch matrix 400 are read out sequentially, the succeeding data input must be queued during this period. Thus, continuous processing is not possible. The circuit network 500 for arranging the read data is also necessary, the fact resulting in a complicated circuit.